As the integration of semiconductor devices has increased, the area occupied by individual devices on a semiconductor substrate (chip) has been reduced. Information storage capacitors for DRAM devices, however, may need to maintain a same or increased capacitance within a reduced area. Accordingly, various methods have been developed to provide increased capacitor electrode surface areas. For example, capacitors having lower electrodes with three-dimensional shapes such as cylindrical shapes or fin shapes have been provided. In addition, hemispheric grains have been coated on surfaces of lower electrodes, thickness of dielectric layers have been reduced, and dielectric layers having high dielectric constants and/or formed of ferroelectric materials have been provided.
When the thickness of a dielectric layer is reduced, leakage currents may occur due to tunneling effects. Accordingly, when a material having high electric constant, such as Ta2O5 or BST ((Ba,Sr)TiO3), is used as a dielectric material, a polysilicon layer may be unsuitable for use as a capacitor electrode. Thus, when a material having a high dielectric constant or a ferroelectric material is used as a dielectric layer, a metal such as platinum (Pt), ruthenium (Ru), iridium (Ir), rhodium (Rh), or osmium (Os), having a high work function, may be used as an electrode material.
A method for manufacturing a conventional Metal-Insulator-Metal (MIM) capacitor will now be discussed with reference to FIGS. 1A and 1B.
Referring to FIG. 1A, a conductive layer 20 for a lower capacitor electrode is deposited on a semiconductor substrate 10. Here, the conductive layer 20 is formed of Pt, Ru, Ir, Rh, or Os. A dielectric layer, such as a tantalum oxide layer 30, is deposited on the conductive layer 20. The tantalum oxide layer 30 is deposited in an amorphous state so that the dielectric characteristics of the tantalum oxide layer 30 may be relatively poor. On the other hand, when the tantalum oxide layer 30 is crystallized, the dielectric constant may increase but leakage current characteristics may deteriorate. Accordingly, after the tantalum oxide layer 30 is deposited, a thermal process for improving the dielectric constant can be performed at a temperature less than that required to crystallize the amorphous tantalum oxide layer 30. Such a curing process can be performed at a temperature of, for example, about 600° C. in a nitrogen atmosphere.
Referring to FIG. 1B, a conductive layer 40 for an upper electrode is deposited on the cured tantalum oxide layer 30. Here, the conductive layer 40 is formed of the same material as the conductive layer 20. Thereafter, to measure the characteristics of a capacitor, the conductive layer 40 and the tantalum oxide layer 30 are dry etched. Thus, a predetermined portion of the conductive layer 20 is exposed. In addition, a thermal process is performed to relieve stress at the interface between the conductive layer 40 and the tantalum oxide layer 30 due to lattice defects. Here, the thermal process for relieving stress is performed at a low temperature of, for example, about 400° C. in an oxygen atmosphere.
However, the thermal processes after depositing the dielectric layer and etching the conductive layer for the upper electrode may complicate the conventional method for manufacturing an MIM capacitor. In other words, since a wafer may need to be transferred for each thermal process, the conventional method may require an increased amount of time, and contaminants may remain on the wafer.